The present invention relates, in general, to electronics and, more particularly, to semiconductor device structures and methods of manufacture.
Metal-oxide semiconductor field effect transistors (MOSFETs) are a common type of power switching device widely used in industry. A MOSFET device includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure provided adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to and separated from the channel region by a thin dielectric layer.
When a MOSFET device is in the on state, a voltage is applied to the gate structure to form a conduction channel region between the source and drain regions, which allows current to flow through the device. In the off state, any voltage applied to the gate structure is sufficiently low so that a conduction channel does not form, and thus current flow does not occur. During the off state, the device must support a high voltage between the source region and the drain region. In the on state, on-state resistance (Rdson) is an important performance parameter, and in the off state, breakdown voltage (BVdss) is an important performance parameter.
FIG. 1 shows a simplified schematic of an example application using MOSFETs in a DC/DC buck regulator configuration 1. DC/DC buck regulators are used to step down voltage (while stepping up current) from the voltage supply to the voltage output. Such configurations are used in, for example, computing applications, game console applications, consumer Point of Load (PoL) applications, as well as others. DC/DC bucker regulator configuration 1 includes a low-side MOSFET 2, a high-side MOSFET 3, a driver device 6, and a pulse width modulation (PWM) device 7. MOSFET 2 includes a source 2A, a drain 2B connected to a ground node 5, and a gate electrode 2C connected to driver 6. MOSFET 3 includes a source 3A connected to a power or supply node 4, a drain 3B connected to source 2A of MOSFET 2, and a gate electrode 3C connected to driver device 6. An output node or switch node 8 is provided between drain 3B and source 2A. Switch node 8 typically is connected to at least one energy storage element, such as a capacitor, an inductor, or a combination of the two, which is configured to provide the desired output voltage.
In the past, the high-side MOSFET 3 and the low-side MOSFET 2 have either been packaged as separate devices, or have been co-packaged on a lead frame with the two devices being disposed in a laterally separated configuration and interconnected with wires or clips. Both of these approaches have had limitations including: increased usage of application board space, decreased efficiency, increased assembly costs, increased interconnect resistance, increased lag time, increased device on-resistance, and increased parasitics, among others.
Accordingly, it is desirable to have a method and structure for assembling power semiconductor devices, such as MOSFET devices. Also, it would be beneficial if the method and structure could provide a low cost means for assembling or configuring a low-side MOSFET and a high-side MOSFET that overcomes the issues identified above as well as others.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current-carrying electrode means an element of a device that carries current through the device, such as a source or a drain of an MOS transistor, an emitter or a collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device, such as a gate of a MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-type regions and certain P-type regions, a person of ordinary skill in the art understands that the conductivity types can be reversed and are also possible in accordance with the present description, taking into account any necessary polarity reversal of voltages, inversion of transistor type and/or current direction, etc. For clarity of the drawings, certain regions of device structures, such as doped regions or dielectric regions, may be illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that, due to the diffusion and activation of dopants or formation of layers, the edges of such regions generally may not be straight lines and that the corners may not be precise angles. Furthermore, the term major surface when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items. In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including, when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof. It will be understood that, although the terms first, second, etc. may be used herein to describe various members, elements, regions, layers and/or sections, these members, elements, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one member, element, region, layer and/or section from another. Thus, for example, a first member, a first element, a first region, a first layer and/or a first section discussed below could be termed a second member, a second element, a second region, a second layer and/or a second section without departing from the teachings of the present disclosure. It will be appreciated by those skilled in the art that words, during, while, and when as used herein related to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as propagation delay, between the reaction that is initiated by the initial action. Additionally, the term while means a certain action occurs at least within some portion of a duration of the initiating action. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but in some cases it may. The use of word about, approximately or substantially means a value of an element is expected to be close to a state value or position. However, as is well known in the art there are always minor variances preventing values or positions from being exactly stated. Unless specified otherwise, as used herein the word over or on includes orientations, placements, or relations where the specified elements can be in direct or indirect physical contact. Unless specified otherwise, as used herein the word overlapping includes orientations, placements, or relations where the specified elements can at least partly or wholly coincide or align in the same or different planes. It is further understood that the embodiments illustrated and described hereinafter suitably may have embodiments and/or may be practiced in the absence of any element that is not specifically disclosed herein.